1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and more specifically, to a method of reducing line edge roughness (LER) of a feature in photoresist.
2. Discussion of Related Art
The manufacturing of IC devices involves the sequential processing of a wafer to form or remove materials for each layer of the wafer. Various materials may be formed by processes, such as oxidation, chemical vapor deposition, sputter deposition, ion implantation, and electroplating. Certain materials may be removed, partially or completely, by processes, such as wet etch, dry etch, or polishing.
Photolithogaphy may be performed together with some of these processes to selectively process certain portions of the wafer. Photolithogaphy may involve about 35 masks to pattern all of the layers on the wafer. However, only those masks which are used for layers that define the features in the IC design having the tightest groundrules are considered critical. The critical layers typically include isolation, gate, contact, and first metal.
A mask may be fabricated by depositing an opaque material, such as chrome, on a transparent substrate, such as quartz, and then etching the chrome to form features that are 4 times larger than the desired size on the wafer.
The wafer is covered with a material called photoresist that is sensitive to radiation. An exposure tool, such as a wafer scanner, optically reduces the features 4 times while projecting radiation of the appropriate wavelength through the mask so as to print a latent image with the correct dimensions on the wafer. Many parameters of an IC device are monitored during fabrication to assure that the device will meet the performance and reliability specifications.
In particular, the performance of a microprocessor is strongly dependent on the channel length of the devices in the microprocessor. The channel length is determined by the critical dimension (CD) of the gate. The processes of photolithography and etch are used to define the gate CD during the fabrication of the microprocessor on a wafer.
The yield in fabricating a microprocessor is strongly impacted by variability in gate CD of the devices formed across the wafer. CD variability includes line edge roughness (LER). As gate CD is progressively scaled down with each new generation of a microprocessor, LER consumes an increasingly larger portion of the overall CD error budget.
Thus, what is needed is a method of reducing line edge roughness of a feature in photoresist.